FIG. 1 shows a cross section of a typical CMOS integrated circuit. The circuit shown and described is a P-Well circuit. However, it will be apparent to those of ordinary skill in the art that this discussion also applies to N-Well circuits by simply interchanging N and P type structures.
An N-type semiconductor substrate 10 is provided for forming the integrated circuit thereon. P-channel devices are formed in the N-type substrate 10 by diffusing or implanting a source 12 and a drain 14. In the circuit of FIG. 1, the source 12 is coupled to a positive voltage supply Vdd. In typical CMOS circuits, a Vdd to substrate contact is formed of an N+diffusion 16.
A P-well 18 is formed in the N type substrate. A drain 20 and a source 22 are formed within the N-well by diffusion or implantation. The source is coupled to Vss. A Vss to substrate contact is formed of a P+diffusion 24 which is also coupled to ground. A P-channel gate 26 is formed over an insulation 28 in the channel region between the source 12 and the drain 14. Similarly, a gate 30 is formed on an insulating layer 32 between the drain 20 and the source 22 of the N-channel transistor in the P-well. This circuit is controlled by a voltage Vin applied to the two gates 26 and 30. The P-channel drain 14 is electrically coupled to the N-channel drain 20. The output of this circuit is a signal formed on the two drains V.sub.o.
A radiation strike (e.g., an .alpha. particle or a heavy ion) in this circuit can induce latch-up of the circuit. Latch-up is a well understood and documented phenomenon resulting from parasitic bipolar transistors. This latch-up condition is a self sustaining high current condition which typically causes thermal runaway, which if let unchecked will permanently damage the circuit. FIG. 2 shows the cross section of FIG. 1 and the parasitic bipolar transistors T1 and T2 coupled as a Silicon Controlled Rectifier (SCR). The transistor T1 is a parasitic PNP transistor. The transistor T2 is a parasitic NPN transistor. The emitter of the transistor T1 is formed of the P+source diffusion 12 of the P-channel transistor. The base of the transistor T1 and the collector of the transistor T2 are formed of the N type substrate 10. The collector of the transistor T1 and the base of the transistor T2 are formed of the P-Well diffusion 18. The emitter of the transistor T2 is formed of the N+source diffusion 22 of the N-channel transistor. A parasitic impedance R.sub.s is formed in the substrate 10 between the base and the emitter of the parasitic PNP transistor T1. A parasitic impedance R.sub.w is formed in the P-Well 18 between the base and emitter of the parasitic NPN transistor T2. FIG. 2B shows the equivalent circuit for the parasitic transistors.
In the event of a radiation strike into the source or drain region of a transistor, the radiation injects current into the base of the PNP transistor T1 causing the transistor to conduct unwanted current and enter the saturation phase of operation. The unwanted current passing through the saturated transistor T1 is driven through the parasitic impedance R.sub.w.
The impedance R.sub.w is coupled across the base-emitter junction of the transistor T2. If the value of the impedance R.sub.w multiplied by the unwanted current is sufficiently high, the voltage across the impedance R.sub.w can exceed the turn on potential for the transistor T2 causing it to conduct current. If the value of the impedance R.sub.s multiplied by the current through the transistor T2 is sufficient to form a voltage large enough to hold the transistor T1 in an active or saturated state latch-up has occurred. Thus, the transistors T1 and T2 now hold each other in an active and latched condition. Typically, normal operation of the circuit can only be recovered by removing the positive voltage supply Vdd.
A second common type of failure in CMOS integrated circuits is the single event upset (SEU) wherein a data bit or logic state in such a device can be corrupted if exposed to an ionized particle such as an .alpha. particle. Current induced by a particle hit flows from N type diffusion to a P type diffusion. Thus, for example, a "1" can be upset in an NMOS static RAM and a "0" can be upset in an PMOS static RAM cell. The design of static RAM cells is clearly described in U.S. Pat. No. 5,111,429 issued May 5, 1992, Sterling R. Whitaker one of the inventors of the present patent application. That patent entitled SINGLE EVENT UPSET HARDENING CMOS MEMORY CIRCUIT is incorporated in its entirety herein by reference.